Field of the Invention
The present invention relates to high density integrated circuit devices. In particular, embodiments according to the present invention provide a method for manufacturing and a structure for a high density device.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been developing techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
In some arrangements, a 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of semiconductor material separated by insulating material. The strips of semiconductor material are horizontal channels of memory cells in NAND strings, for example. One configuration, including these features referred to as a 3D Vertical Gate (3DVG) architecture, is described below with reference to FIG. 1. See, U.S. Pat. No. 8,503,213, entitled Memory Architecture of 3D Array with Alternating Memory String Orientation and String Select Structures, issued 6 Aug. 2013, by inventors Shih-Hung Chen and Hang-Ting Lue.
Another structure that provides vertical channel, NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes a vertical channel, horizontal gate NAND, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a vertical channel, gate-all-around GAA cell at each layer.
In other embodiments, vertical channels (or NAND bit lines) can be disposed between the strips for vertical NAND string configurations. See for example, U.S. Pat. No. 8,363,476, issued 29 Jan. 2013 (filed 19 Jan. 2011), entitled Memory Device, Manufacturing Method And Operating Method Of The Same, by inventors Hang-Ting Lue and Shi-Hung Chen, which is incorporated by reference as if fully set forth herein.
A number of technologies have been pursued to improve the structure of 3D arrays and the processes for making them, as disclosed in U.S. patent application Ser. No. 13/935,375 filed on 3 Jul. 2013, entitled Damascene Conductor for a 3D Device, by inventors Chia-Jung Chiu and Guanru Lee; and U.S. patent application Ser. No. 14/029,305 filed on 17 Sep. 2013, entitled Conductor with a Plurality of Vertical Extensions for a 3D Device, by inventors Yen-Hao Shih and Hang-Ting Lue; which are incorporated by reference as if fully set forth herein.
The formation of conductive lines that include vertical columns between ridges in high aspect ratio trenches, such as those used in the 3DVG architecture, the vertical NAND architectures and other high density structures, can require complex patterning technologies. The ridge-like stacks formed using trenching techniques can be very narrow. However, the ridge-like stacks can bend or wiggle during the manufacturing process. These problems and other problems associated with the formation of high density stacks can reduce yield.
It is desirable to provide memory cell technologies and technologies for formation of word lines and bit lines for accessing the memory cells, of the type that can be used in complex 3D structures.